Objective
Our objective is to become one of the most reliable digital VLSI design service providers in Industry and expanding with the key contacts in the industry to offer cutting-edge services by building reputation with transparency and seamless collaboration. We believe in teamwork as strength for its growth & success.
Our aim is to contribute and promote the advancement of all aspects of VLSI technology by all suitable means. Our people are our strongest asset, and we are passionate about making a definitive impact in all we do.
Mission & Vision
PD (Physical Design): SpiderChip's expert Team will provide support throughout RTL to GDSII stages of ASIC design flow. Our team has extensive experience in advanced flows for power aware synthesis (UPF, CPF), timing constraint generation (STA), netlist floor planning for best possible PPA and place and route(PNR) for overcoming ever increasing complexity. Our engineers in-depth knowledge of EDA tools and scripting skills enable us to deliver full turn-key ASIC development.
STA (Static Timing Analysis) is one of the most important area in Semiconductor chip Designing. Having an in-depth knowledge and exposure in STA provides opportunity in exploring and understanding how other domains operate to design chip. As expert say Timing and Performance is almost everything, STA turns out to be the single most important domain which collaborates with every other areas of chip designing. SpiderChip Team can help to meet customer requirements and deliver as per expectations.
PV (Physical Verification): SpiderChip’s verification team has proven expertise on taking complete ownership of verification. Verification is one of the key issues in IC design and development impacting product schedules and timelines. We offers a wide range of ASIC verification services to help customers, especially physical verification checks like DRC, LVS, ERC, DFM, ESD, Antenna etc
Analog Layout: SpiderChip Layout team has extensive experience in high speed and core analog layout. Our team has in-depth expertise on variety of IPs such as SerDes (10, 16, 30 & 56 Gbps), DDRphy, USB 2.0, MIPIphy and Power management. We have also handled expanded portfolios of Data converters, clock circuits such as PLL, DLL & oscillators, Regulators, Bias, Bandgap references, Temperature sensors, UVLOs etc SpiderChip Team has proven experience on different process nodes to the cutting edge technology: Planar (180nm, 130nm, 110nm, 65nm, 55nm, 45nm, 40nm, 32nm, 28nm, 20nm and more) and Finfet (16nm/14nm, 12nm, 10nm, 7nm, 6nm, 5nm) with foundry TSMC, Samsung, UMC, GF and Intel. Multiple full chip and IP level tape out has been successfully done with first pass silicon.
Design Verification: SpiderChip has one of industry’s strongest teams in design verification. Our team can execute verification from scratch of complex SoC’s and IP’s by using latest methodologies such as SV-UVM, UPF and meeting key KPI such as 100% functional and code coverage Advanced IP & SoC Verification. We also provide silicon proven VIP for latest IP’s and provide source code and aftersales support to our customers.
Key Skills
