Logic/Physical Synthesis
IO ring preparation & Bump planning
Timing Constraints Preparation and Validation
Floorplan & power planning
Clock Tree Synthesis
Place and route
Low power implementation
Static Timing Analysis
Signal Integrity
IR drop Analysis and Repair
Physical Verification like DRC, LVS, Antenna, Density, ERC etc
ECO implementation
Sign-Off and Tapeout
Industry Standard EDA Tools: Synopsys, Cadence, Mentor
Physical Design (PD)
Our Services
Static Timing Analysis (STA)
Process Variation and related Margins
Peripheral Interface protocols and timing
Mission mode and Test mode Constraints (Data flow)
High Speed Clocking Architecture
Synchronous/Asynchronous designs
Signal Integrity
Physical Verification (PV)
Analog Layout
Design Verification (DV)
Design Rule Check (DRC)
Base & Metal DRC
Layout versus Schematic (LVS)
LVS Flow, Input Requirements, checks, errors
Electrical Rule Check (ERC)
Lithography Process Checking
Antenna Checks
Latch-up
Reliability checks like EM and IR analysis
Double pattern checks
Design for manufacturability (DFM) checks
Electrostatic discharge (ESD) path checks
Understanding the design specification document and creating the test plan
Creating the complete verification environment using industry standard methodologies like UVM/OVM/VMM
Gate level simulations
Verification closure through corner case verification, coverage closure and regression closure
Advanced IP & SoC Verification
SV-UVM Based Constrained - Random Verification
Low Power Verification
Assertion based Verification, System verilog assertions
Palladium, Zebu & Veloce based Validation Silicon validation
Experts with experience down to 7nm process node
Floor planning, BUMP routing and Area optimization
Analog layout matching/shielding techniques
IR drop and EM analysis
ESD & clamps placement
Complex Mixed signal integration
Layout verification flows : DRC, LVS, Extraction, DFM, EM & IR